With higher signal frequencies being utilized in communication systems and integrated circuits, there is a great demand for low-cost, miniature microwave components. In many applications, such components must be integrated with analog and digital circuits. Various techniques have been proposed for fabricating microwave components using micromachining techniques. These proposed techniques, however, require many photolithographic masking steps both on the top and bottom surfaces of the wafer for micromachining and metal deposition. The techniques are not compatible with commercially available CAD tools and CMOS foundry capabilities. Consequently, integration of such components with analog and digital circuits using conventional techniques is not possible.
Generally, standard CMOS silicon ICs are not suitable for integration of microwave components due to high losses in silicon at microwave frequencies. The removal of the lossy silicon substrate material in the vicinity of the metal structures, however, significantly improves the insertion loss characteristics, transmission line dispersion characteristics, phase velocity, and impedance control capability. Thus, a class of passive microwave components can be integrated into the CMOS integrated circuits. Further, the structures are fully compatible with commercial CAD tools, fabrication using commercial CMOS foundry services or the MOSIS services, and micromachined with no additional photolithographic steps.
For these reasons, it is of interest to remove the silicon substrate from directly beneath the thermal and microwave structures to improve the above-described characteristics, while still allowing the monolithic integration of CMOS electronics and overall low-cost fabrication sensors.
FIG. 1 is a cross-sectional view showing the result of an isotropic etching through one opening in a thin film layer covering a substrate. Substrate 7, for example a silicon substrate, includes thin film 42, opening 40, and cavity 21. During isotropic etching, a gaseous etchant, such as xenon difluoride (XeF.sub.2), is typically used to create a cavity 21 directly underneath the opening 40 which propagates outward radially. Thin film 42, covering the top of silicon substrate 7, acts as an etch resistant mask protecting the uncovered portion of silicon substrate 7. However, one problem that exists with this method of etching is that all cavities formed are hemispherical in shape. This places constraints on device designs that result in the prevention of fabrication of the desired device structures.
FIG. 2 is a cross-sectional view showing the result of isotropic etching through multiple openings in a thin film layer covering a substrate. Substrate 7, for example a silicon substrate, includes thin film portions 42 and 42a, openings 40a and 40b, and cavities 21a and 21b. Similarly, an isotropic etchant, such as xenon difluoride (XeF.sub.2), is used to create multiple cavities 21a and 21b directly underneath the multiple openings 40a and 40b, wherein the cavities propagate outward radially. If etching continues long enough, cavities 21a and 21b eventually merge, forming a single cavity 21 which suspends a portion 42a of film 42. Thus, a device may be suspended above merged cavities 21a and 21b. One problem with this solution is that the suspended portion is limited in size. Additionally, limitations are placed on device layouts, and the bottom of the cavity is not entirely flat.
FIG. 3 is a cross-sectional view showing the result of etching using an anisotropic etchant through an opening in a masking thin film layer covering a substrate. Substrate 7, for example a silicon substrate, includes etch resistant masking thin film 42, opening 40, and V-shaped cavity 21. An anisotropic etchant, such as ethylene diamine-pyrocatechol-water (EDP), is used to create a V-shaped cavity 21 directly underneath opening 40. The anisotropic etch follows the crystalline structure of the &lt;100&gt; wafer, for example, wherein side walls 21c and 21d of V-shaped cavity 21 are typically at a slope of 54.7 degrees from the surface plane (i.e. film 42) and are aligned to the &lt;111&gt; crystallographic plane of substrate 7. Similarly, a problem with this method is that the suspended portion is limited in size.